MARVELL 88E1512 DRIVER

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With the Alaska family, Marvell delivers a new class of Gigabit PHYs designed to meet the demands of next-generation green networks. Alaska Gigabit Ethernet Designed to meet the demands of next generation green networks. It’s not being released in the petalinux Careers at Marvell Marvell offers a collaborative fast-paced environment where innovative ideas can really make a difference. However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1:

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msrvell It’s not being released in the petalinux What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct drivers from petalinux? I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond.

I don’t have the Marvell datasheet handy, but recall seeing that when run a 1.

I assume you use the same interface voltage for both PHY chips. Haven’t worked on this in a couple of years.

Again, this appears to be a software issue. We are not able to run our dual GEM config. I haven’t used Zynq before, so maybe this suggestion is not appropriate.

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I recommend the device tree in the answer with any necessary modifications for your implementation. We have detected your current browser version is not the latest one. With linux this indeed is a problem, when doing it correctly in devicetree then lots marvel, errors come during boot, claiming PHY 0 is invalid, then PHY 0 is 88s1512, and working, and the second PHY with address 1 valid address remains not configured and is fully not accessible.

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88EA0-NNP2I Marvell | Ciiva

Thanks for the information. Check the reset pin to the PHYs. Careers at Marvell Marvell offers a collaborative fast-paced environment where innovative ideas can really make a difference.

Looking for our Products? However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth I enable eth0 and see transactions on the MDIO bus.

Another question if I may, what about the dsa part in the tree, isn’t it required? I Have met the same problem, hope could get some ideas from you! Please upgrade to a Xilinx.

I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly. The software doesn’t seem to do anything with it. Quickly and easily view product specs, compare various solutions, and print out select product information. Additional features of the Alaska GbE PHYs include a high-level of integration in thermally-efficient packages that optimize PCB real estate and enable fan-less heat-sink-less designs.

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Do you have any further information about this question? The Alaska Gigabit PHYs build on the Marvell legacy of providing unique, best-in-class features that enable customers to expand their Ethernet applications. Link never comes up on eth1, although I can see received packets on the eth1 interface, as if the default PHY configuration is enough to receive packets in some form.

Alaska Gigabit Ethernet PHYs Transceivers

I have tried that previously and once againt to verify. All forum topics Previous Topic Next Topic. Add the phy handle to the gem sections: Give Kudos to a post which you think is helpful and reply oriented. Patch is applicable ONLY to the Ethics Supplier Responsibility Environment Community.